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[Peter da Silva: Re: Why do RISCs use (*not* need) fewer transistors?]
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To: yucks
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Subject: [Peter da Silva: Re: Why do RISCs use (*not* need) fewer transistors?]
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From: Gene Spafford <spaf>
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Date: Sun, 16 Dec 90 11:34:08 EST
There is definitely some amusement factor here, but this is probably
only for the serious "bit-head". (If you don't fit that label, skip
to the end and read Peter's signature :-)
------- Forwarded Message
In comp.arch, article <276A5ADC.23D7@wilbur.coyote.trw.com>,
Robert Heiss (rob@wilbur.coyote.trw.com) wrote:
In article <1990Dec15.021854.7613@d.cs.okstate.edu> minich@d.cs.okstate.edu (Ro
bert Minich) writes:
>by rcpieter@svin02.info.win.tue.nl (Tiggr):
>| The ARM is a good example of a RISC with very few transistors (core is < .5k
>| transistors). The reason is that its designers wanted it to be CHEAP.
>
> Wow, 500 transistors for the core. Must be one of those RidiculISC
>extremists. :-)
Okay, the software engineers demand a 32 bit processor, and the bean
counters give a 500 transistor budget. Overconstrained? Let's give
it a try.
A bit serial approach is selected. This results in meager instruction
throughput, but makes possible an extremely high clock rate. Since most
of your market believes computer horsepower is measured in MHz, sales
will take off. The sluggish performance will have them back as repeat
customers within a year.
The serial adder with carry flip-flop is just a few dozen transistors.
Data path multiplexers and logical instructions cost four transistors each.
Special locations in main memory will substitute for operand registers.
So far it looks like 500 will be easy. Unfortunately we need a full size
memory address register to form those 32 bit addresses for the bloated
software. A 32 bit instruction pointer probably requires a hardware
register too, but we can economize by storing it on dynamic nodes next
to the memory address register. The control section has a 6 bit
counter to keep track of all those shifting microcycles.
Instructions. Let's splurge and have four independent ones: ADD, NOR,
STORE, and JMPNEG. One addressing mode: direct. The hardware will need
just 2 bits of instruction register, and the rest of the instruction
format can gate directly into the memory address register. Oops, that's
looks like only 30 bits of word addressability. Here a byte, there a
shift, and in come the orders for the commercial instruction set option.
The customer's consultants must never see the raw hardware instruction
set. Some of them would complain bitterly about having to teach the
computer to subtract, multiply, and divide (probably because they don't
remember how) and our machine could get an unfavorable reputation. Base
level assembly language is verbose, convoluted and ugly. Wrap two layers
of microcode around the machine to emulate a sophisticated instruction
set.
The first layer of microcode emulates arithmetic, stack, index registers,
and memory mapping. Level 1 assembly language is concise and effective.
The second layer of microcode implements call gates, virtual machines,
capabilities, and something we can call object oriented. Level 2 assembly
language is verbose, convoluted, and ugly, but the consultants would feel
like members of a high priesthood.
PUTTING IT ALL TOGETHER
Function Bits@Trans Subtotal
full-adder 1@28 28
nor 1@4 4
shift-register 33@8 264
dynamic-latch 33@2 66
multiplexers 40@2 80
counter 6@18 108
control-pla n/a 100 est.
Total Transistors 650
The design is running 30% over budget. The bean counter wants to compare
die size against the competition to see if they have a cost advantage.
i486 Die:
+--------------------------------------------------------------------+
| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
|0################################################################## |
| ##################################################################0|
| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
+--------------------------------------------------------------------+
SPARC Die:
+-----------------------------+
| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
|0###########################0|
| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
+-----------------------------+
500T Die:
+-------------+
| 00000000000 |
|0 0|
|0 0|
|0 0|
|0 # 0|
|0 0|
|0 0|
|0 0|
| 00000000000 |
+-------------+
Our yield is expected to be quite good. Note that the die size is limited
by the bond pads for the address bus. There is opportunity for a cost-
reduced variant with multiplexed address bus.
500SX Die:
+---+
| 0 |
|0#0|
| 0 |
+---+
The bean counter is ecstatic! Yield is 99.9% and a tested die costs only .3
cents. In quantity 10000 it sells for less than a bypass capacitor. The
package looks like a transistor. Rumor has it that some are marked 2N500SX
to get around the export ban to the Soviet Union.
Robert Heiss rob@wilbur.coyote.trw.com
- ---
Peter da Silva. `-_-' "Eat hot digital death, mainframe scum!"
+1 713 274 5180. 'U` -- Attack of the Killer Micros.
peter@ferranti.com Part II: Revenge of the IO Masters.
------- End of Forwarded Message